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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccel/HsuLB24>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pei-Jun_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Trong-An_Bui>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Chen_Hsu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCE59016.2024.10444458>
foaf:homepage <https://doi.org/10.1109/ICCE59016.2024.10444458>
dc:identifier DBLP conf/iccel/HsuLB24 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCE59016.2024.10444458 (xsd:string)
dcterms:issued 2024 (xsd:gYear)
rdfs:label Efficient FPGA-Accelerated Neural Network Scalable Upsampling Architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pei-Jun_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Trong-An_Bui>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Chen_Hsu>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccel/2024>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccel/HsuLB24/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccel/HsuLB24>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccel/icce2024.html#HsuLB24>
rdfs:seeAlso <https://doi.org/10.1109/ICCE59016.2024.10444458>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccel>
dc:title Efficient FPGA-Accelerated Neural Network Scalable Upsampling Architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document