Design and Implementation of Frequency Offset Estimation, Symbol Timing and Sampling Clock Offset Control for an IEEE 802.11a Physical Layer. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kwang_Ho_Chun>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Myoung-ho_Seong>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Myoung_Seob_Lim>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Seung-hyun_Min>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1007%2F11424826%5F76>
foaf:homepage	<https://doi.org/10.1007/11424826_76>
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dcterms:issued	2005 (xsd:gYear)
rdfs:label	Design and Implementation of Frequency Offset Estimation, Symbol Timing and Sampling Clock Offset Control for an IEEE 802.11a Physical Layer. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Myoung_Seob_Lim>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Seung-hyun_Min>
swrc:pages	723-731 (xsd:string)
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dc:title	Design and Implementation of Frequency Offset Estimation, Symbol Timing and Sampling Clock Offset Control for an IEEE 802.11a Physical Layer. (xsd:string)
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