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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccsce/LohLS22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jia_Jia_Sim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Siu_Hong_Loh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/You_Hong_Liew>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICCSCE54767.2022.9935582>
foaf:homepage <https://doi.org/10.1109/ICCSCE54767.2022.9935582>
dc:identifier DBLP conf/iccsce/LohLS22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICCSCE54767.2022.9935582 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM). (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jia_Jia_Sim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Siu_Hong_Loh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/You_Hong_Liew>
swrc:pages 7-12 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iccsce/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccsce/LohLS22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccsce/LohLS22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccsce/iccsce2022.html#LohLS22>
rdfs:seeAlso <https://doi.org/10.1109/ICCSCE54767.2022.9935582>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iccsce>
dc:title VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document