FPGA implementation of an MLSE equalizer in 10Gb/s optical links.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icdsp/StamouliasGBG15
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/icdsp/StamouliasGBG15
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/George-Othon_Glentis
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ioannis_Stamoulias
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kristina_Georgoulakis
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/S._Blionas
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICDSP.2015.7251985
>
foaf:
homepage
<
https://doi.org/10.1109/ICDSP.2015.7251985
>
dc:
identifier
DBLP conf/icdsp/StamouliasGBG15
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICDSP.2015.7251985
(xsd:string)
dcterms:
issued
2015
(xsd:gYear)
rdfs:
label
FPGA implementation of an MLSE equalizer in 10Gb/s optical links.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/George-Othon_Glentis
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ioannis_Stamoulias
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kristina_Georgoulakis
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/S._Blionas
>
swrc:
pages
794-798
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/icdsp/2015
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/icdsp/StamouliasGBG15/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/icdsp/StamouliasGBG15
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/icdsp/icdsp2015.html#StamouliasGBG15
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICDSP.2015.7251985
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/icdsp
>
dc:
title
FPGA implementation of an MLSE equalizer in 10Gb/s optical links.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document