A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Chiou-Bang_Chen>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Horng-Yuan_Shih>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICECS.2010.5724452>
foaf:homepage	<https://doi.org/10.1109/ICECS.2010.5724452>
dc:identifier	DBLP conf/icecsys/ChenS10 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICECS.2010.5724452 (xsd:string)
dcterms:issued	2010 (xsd:gYear)
rdfs:label	A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Chiou-Bang_Chen>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Horng-Yuan_Shih>
swrc:pages	53-56 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/icecsys/icecsys2010.html#ChenS10>
rdfs:seeAlso	<https://doi.org/10.1109/ICECS.2010.5724452>
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dc:title	A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process. (xsd:string)
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