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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icecsys/DioquinoRSZBR08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anastacia_P._Ballesil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Darryl_Aldrin_M._Dioquino>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Homer_F._Supe>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jestoni_V._Zarsuela>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joy_Alinda_Reyes>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Katrina_Joy_S._Rosario>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICECS.2008.4674891>
foaf:homepage <https://doi.org/10.1109/ICECS.2008.4674891>
dc:identifier DBLP conf/icecsys/DioquinoRSZBR08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICECS.2008.4674891 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anastacia_P._Ballesil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Darryl_Aldrin_M._Dioquino>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Homer_F._Supe>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jestoni_V._Zarsuela>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joy_Alinda_Reyes>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Katrina_Joy_S._Rosario>
swrc:pages 466-469 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ICECS.2008.4674891>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icecsys>
dc:title DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document