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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icecsys/GreenbergBHM04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Avishay_Maman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ido_Bloch>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Moti_Horwitz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shlomo_Greenberg>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICECS.2004.1399707>
foaf:homepage <https://doi.org/10.1109/ICECS.2004.1399707>
dc:identifier DBLP conf/icecsys/GreenbergBHM04 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICECS.2004.1399707 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Avishay_Maman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ido_Bloch>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Moti_Horwitz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shlomo_Greenberg>
swrc:pages 419-423 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icecsys/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icecsys/GreenbergBHM04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icecsys/GreenbergBHM04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icecsys/icecsys2004.html#GreenbergBHM04>
rdfs:seeAlso <https://doi.org/10.1109/ICECS.2004.1399707>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icecsys>
dc:title Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document