Power, Performance and Area Optimization of Parallel Load Counters through Logic Minimization and TSPC-FF Utilization.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icecsys/HumoodSWP23
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Power, Performance and Area Optimization of Parallel Load Counters through Logic Minimization and TSPC-FF Utilization.
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Power, Performance and Area Optimization of Parallel Load Counters through Logic Minimization and TSPC-FF Utilization.
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