Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icecsys/KerJPS01
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Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's.
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Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's.
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