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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icecsys/NicolleGFTJ05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Benjamin_Nicolle>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Emeric_de_Foucauld>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gilles_Jacquemod>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lionel_Geynet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/William_Tatinian>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICECS.2005.4633374>
foaf:homepage <https://doi.org/10.1109/ICECS.2005.4633374>
dc:identifier DBLP conf/icecsys/NicolleGFTJ05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICECS.2005.4633374 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label VHDL-AMS modeling of a multi-standard phase locked loop. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Benjamin_Nicolle>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Emeric_de_Foucauld>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gilles_Jacquemod>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lionel_Geynet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/William_Tatinian>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icecsys/2005>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icecsys/icecsys2005.html#NicolleGFTJ05>
rdfs:seeAlso <https://doi.org/10.1109/ICECS.2005.4633374>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icecsys>
dc:title VHDL-AMS modeling of a multi-standard phase locked loop. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document