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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Teresa_Serrano-Gotarredona>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICECS.2012.6463504>
foaf:homepage <https://doi.org/10.1109/ICECS.2012.6463504>
dc:identifier DBLP conf/icecsys/Serrano-GotarredonaL12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICECS.2012.6463504 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label Design of adaptive nano/CMOS neural architectures. (xsd:string)
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swrc:pages 949-952 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ICECS.2012.6463504>
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dc:title Design of adaptive nano/CMOS neural architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document