A low power NORA circuit design technique based on charge recycling. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Angela_Arapoyanni>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Konstantinos_Limniotis>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Themistoklis_Haniotakis>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yiorgos_Tsiatouhas>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICECS.2003.1302017>
foaf:homepage	<https://doi.org/10.1109/ICECS.2003.1302017>
dc:identifier	DBLP conf/icecsys/TsiatouhasLAH03 (xsd:string)
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dcterms:issued	2003 (xsd:gYear)
rdfs:label	A low power NORA circuit design technique based on charge recycling. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Angela_Arapoyanni>
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Themistoklis_Haniotakis>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Yiorgos_Tsiatouhas>
swrc:pages	224-227 (xsd:string)
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dc:title	A low power NORA circuit design technique based on charge recycling. (xsd:string)
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