Circuit synthesis based on VHDL language transformations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icecsys/VargaHK99
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/icecsys/VargaHK99
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ferenc_Kov%E2%88%9A%C2%B0cs
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/G%E2%88%9A%C2%B0bor_Hossz%E2%88%9A%C4%BC
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/L%E2%88%9A%C2%B0szl%E2%88%9A%E2%89%A5_Varga_0003
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICECS.1999.812264
>
foaf:
homepage
<
https://doi.org/10.1109/ICECS.1999.812264
>
dc:
identifier
DBLP conf/icecsys/VargaHK99
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICECS.1999.812264
(xsd:string)
dcterms:
issued
1999
(xsd:gYear)
rdfs:
label
Circuit synthesis based on VHDL language transformations.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ferenc_Kov%E2%88%9A%C2%B0cs
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/G%E2%88%9A%C2%B0bor_Hossz%E2%88%9A%C4%BC
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/L%E2%88%9A%C2%B0szl%E2%88%9A%E2%89%A5_Varga_0003
>
swrc:
pages
225-228
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/icecsys/1999
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/icecsys/VargaHK99/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/icecsys/VargaHK99
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/icecsys/icecsys1999.html#VargaHK99
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICECS.1999.812264
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/icecsys
>
dc:
title
Circuit synthesis based on VHDL language transformations.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document