Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icecsys/WuW04
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Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.
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Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.
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