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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ices/WangPL07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chang_Hao_Piao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chong_Ho_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jin_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-74626-3%5F3>
foaf:homepage <https://doi.org/10.1007/978-3-540-74626-3_3>
dc:identifier DBLP conf/ices/WangPL07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-74626-3%5F3 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chang_Hao_Piao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chong_Ho_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jin_Wang>
swrc:pages 23-34 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ices/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ices/WangPL07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ices/WangPL07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ices/ices2007.html#WangPL07>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-74626-3_3>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ices>
dc:subject Intrinsic evolvable hardware; scalability; parallel evolutionary algorithm; incremental evolution (xsd:string)
dc:title Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document