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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andy_M._Tyrrell>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_Alfred_Walker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Martin_A._Trefzer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Simon_J._Bale>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yang_Xiao_0008>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICES.2014.7008715>
foaf:homepage <https://doi.org/10.1109/ICES.2014.7008715>
dc:identifier DBLP conf/ices/XiaoWBTT14 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICES.2014.7008715 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label Circuit design optimisation using a modified genetic algorithm and device layout motifs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andy_M._Tyrrell>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_Alfred_Walker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Martin_A._Trefzer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Simon_J._Bale>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yang_Xiao_0008>
swrc:pages 1-8 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ices/2014>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ices/XiaoWBTT14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ices/XiaoWBTT14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ices/ices2014.html#XiaoWBTT14>
rdfs:seeAlso <https://doi.org/10.1109/ICES.2014.7008715>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ices>
dc:title Circuit design optimisation using a modified genetic algorithm and device layout motifs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document