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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ices/ZhuLHX07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guoliang_He>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jixiang_Zhu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xuewen_Xia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuanxiang_Li_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-74626-3%5F4>
foaf:homepage <https://doi.org/10.1007/978-3-540-74626-3_4>
dc:identifier DBLP conf/ices/ZhuLHX07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-74626-3%5F4 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label An Intrinsic Evolvable Hardware Based on Multiplexer Module Array. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guoliang_He>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jixiang_Zhu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xuewen_Xia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuanxiang_Li_0001>
swrc:pages 35-44 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ices/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ices/ZhuLHX07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ices/ZhuLHX07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ices/ices2007.html#ZhuLHX07>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-74626-3_4>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ices>
dc:subject intrinsic; digital; multiplexer; FPGA (xsd:string)
dc:title An Intrinsic Evolvable Hardware Based on Multiplexer Module Array. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document