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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icess/WangBHYZW05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinian_Bian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Liu_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiang_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhou_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xianlong_Hong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yunfeng_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11599555%5F28>
foaf:homepage <https://doi.org/10.1007/11599555_28>
dc:identifier DBLP conf/icess/WangBHYZW05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11599555%5F28 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinian_Bian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Liu_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiang_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhou_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xianlong_Hong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yunfeng_Wang>
swrc:pages 275-286 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icess/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icess/WangBHYZW05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icess/WangBHYZW05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icess/icess2005.html#WangBHYZW05>
rdfs:seeAlso <https://doi.org/10.1007/11599555_28>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icess>
dc:title A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document