Design and Implementation of High Speed, Low Area Multiported Loadless 4T Memory Cell.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icetet/YagainPKG11
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/icetet/YagainPKG11
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Akriti_Kedia
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ankit_Parakh
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Deepa_Yagain
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Gunjan_Kumar_Gupta
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICETET.2011.23
>
foaf:
homepage
<
https://doi.org/10.1109/ICETET.2011.23
>
dc:
identifier
DBLP conf/icetet/YagainPKG11
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICETET.2011.23
(xsd:string)
dcterms:
issued
2011
(xsd:gYear)
rdfs:
label
Design and Implementation of High Speed, Low Area Multiported Loadless 4T Memory Cell.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Akriti_Kedia
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ankit_Parakh
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Deepa_Yagain
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Gunjan_Kumar_Gupta
>
swrc:
pages
268-273
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/icetet/2011
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/icetet/YagainPKG11/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/icetet/YagainPKG11
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/icetet/icetet2011.html#YagainPKG11
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICETET.2011.23
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/icetet
>
dc:
title
Design and Implementation of High Speed, Low Area Multiported Loadless 4T Memory Cell.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document