Minimize the delay of parasitic capacitance and modeling in RLC circuit.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ichit/LeeBLLKPJ09
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2009
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Minimize the delay of parasitic capacitance and modeling in RLC circuit.
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Elmore, delay, interconnection, oscillator, parasitic capacitance
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Minimize the delay of parasitic capacitance and modeling in RLC circuit.
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