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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icic/LinWYC07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Che-Wei_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun-Chang_Yu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jeen-Shing_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ting-Yu_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-74205-0%5F19>
foaf:homepage <https://doi.org/10.1007/978-3-540-74205-0_19>
dc:identifier DBLP conf/icic/LinWYC07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-74205-0%5F19 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Che-Wei_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun-Chang_Yu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jeen-Shing_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ting-Yu_Chen>
swrc:pages 164-173 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icic/2007-2>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icic/LinWYC07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icic/LinWYC07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icic/icic2007-2.html#LinWYC07>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-74205-0_19>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icic>
dc:subject Synchronous pipeline design; neuro-fuzzy circuit; FPGA (xsd:string)
dc:title Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document