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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iciis/AsatiC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhijit_R._Asati>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chandrashekhar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICIINFS.2008.4798406>
foaf:homepage <https://doi.org/10.1109/ICIINFS.2008.4798406>
dc:identifier DBLP conf/iciis/AsatiC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICIINFS.2008.4798406 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label An improved high speed fully pipelined 500 MHz 8√ó8 baugh wooley multiplier design using 0.6 őľm CMOS TSPC logic design style. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhijit_R._Asati>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chandrashekhar>
swrc:pages 1-6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iciis/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iciis/AsatiC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iciis/AsatiC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iciis/iciis2008.html#AsatiC08>
rdfs:seeAlso <https://doi.org/10.1109/ICIINFS.2008.4798406>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iciis>
dc:title An improved high speed fully pipelined 500 MHz 8√ó8 baugh wooley multiplier design using 0.6 őľm CMOS TSPC logic design style. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document