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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iciis/ShuklaSMT16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ganga_Ram_Mishra>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/O._P._Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Raj_Kumar_Tiwari>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vandana_Shukla>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICIINFS.2016.8262959>
foaf:homepage <https://doi.org/10.1109/ICIINFS.2016.8262959>
dc:identifier DBLP conf/iciis/ShuklaSMT16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICIINFS.2016.8262959 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ganga_Ram_Mishra>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/O._P._Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Raj_Kumar_Tiwari>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vandana_Shukla>
swrc:pages 323-328 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iciis/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iciis/ShuklaSMT16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iciis/ShuklaSMT16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iciis/iciis2016.html#ShuklaSMT16>
rdfs:seeAlso <https://doi.org/10.1109/ICIINFS.2016.8262959>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iciis>
dc:title Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document