A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icip/LaiCTW97
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1997
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A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation.
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VLSI; flexible high-throughput VLSI architecture; 2D data-reuse; full-search motion estimation; data-interlacing architecture; full-search block-matching algorithm; one-dimensional processing element array; data-interlacing shift-register arrays; external memory accesses; pin counts; block sizes; search ranges; pixel rates
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A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation.
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