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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icip/PechanekSVG95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._John_Glossner>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerald_G._Pechanek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/M._Stojancic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stamatis_Vassiliadis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICIP.1995.529041>
foaf:homepage <https://doi.org/10.1109/ICIP.1995.529041>
dc:identifier DBLP conf/icip/PechanekSVG95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICIP.1995.529041 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label MFAST: a single chip highly parallel image processing architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._John_Glossner>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerald_G._Pechanek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/M._Stojancic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stamatis_Vassiliadis>
swrc:pages 69-72 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icip/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icip/PechanekSVG95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icip/PechanekSVG95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icip/icip1995-1.html#PechanekSVG95>
rdfs:seeAlso <https://doi.org/10.1109/ICIP.1995.529041>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icip>
dc:subject parallel architectures; video signal processing; digital signal processing chips; discrete cosine transforms; hardware description languages; real-time systems; MFAST; single chip highly parallel image processing architecture; IBM Mwave; graphics processing; real-time video processing; scalable array of processing elements; folded array; transpose operations; matrix operations; Mwave Folded Array Signal Transform processor; scalable DSP; algorithm execution; 2D DCT program; VHDL; functional simulator models; discrete cosine transform; 16 bit/s; 50 MHz (xsd:string)
dc:title MFAST: a single chip highly parallel image processing architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document