Hardware Implementation of Floating Point Matrix Inversion Modules on FPGAs.
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Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/icm2/ChetanMLS20
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/J._Manikandan
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/S._Chetan
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/S._Sudhakar
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/V._Lekshmi
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICM50269.2020.9331796
>
foaf:
homepage
<
https://doi.org/10.1109/ICM50269.2020.9331796
>
dc:
identifier
DBLP conf/icm2/ChetanMLS20
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICM50269.2020.9331796
(xsd:string)
dcterms:
issued
2020
(xsd:gYear)
rdfs:
label
Hardware Implementation of Floating Point Matrix Inversion Modules on FPGAs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/J._Manikandan
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/S._Chetan
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/S._Sudhakar
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/V._Lekshmi
>
swrc:
pages
1-4
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/icm2/2020
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/icm2/ChetanMLS20/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/icm2/ChetanMLS20
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/icm2/icm2020.html#ChetanMLS20
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICM50269.2020.9331796
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/icm2
>
dc:
title
Hardware Implementation of Floating Point Matrix Inversion Modules on FPGAs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document