Architecture for area-efficient 2-D transform in H.264/AVC.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icmcs/KuoLLJ05
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Architecture for area-efficient 2-D transform in H.264/AVC.
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matrix multiplication, VLSI technology, very large scale integration, ASIC, application-specific integrated circuit, architecture shrinking, minimization, 2-D transform, H.264-AVC, automatic volume control, CMOS technology
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Architecture for area-efficient 2-D transform in H.264/AVC.
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