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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icpads/LiuSC96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chang-Chung_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chung-Ping_Chung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R.-Ming_Shiu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICPADS.1996.517580>
foaf:homepage <https://doi.org/10.1109/ICPADS.1996.517580>
dc:identifier DBLP conf/icpads/LiuSC96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICPADS.1996.517580 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Register renaming for x86 superscalar design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chang-Chung_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chung-Ping_Chung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R.-Ming_Shiu>
swrc:pages 336-343 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icpads/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icpads/LiuSC96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icpads/LiuSC96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icpads/icpads1996.html#LiuSC96>
rdfs:seeAlso <https://doi.org/10.1109/ICPADS.1996.517580>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icpads>
dc:subject microprocessor chips; parallel architectures; register renaming; Intel x86 superscalar design; storage conflicts; instruction level parallelism; data lengths; register write; register read; hardware renaming schemes; aggressive superscalar machine model; simulation results (xsd:string)
dc:title Register renaming for x86 superscalar design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document