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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icpads/XueSLQS06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun_Xue>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Edwin_Hsing-Mean_Sha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mei_Kang_Qiu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Meilin_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zili_Shao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICPADS.2006.58>
foaf:homepage <https://doi.org/10.1109/ICPADS.2006.58>
dc:identifier DBLP conf/icpads/XueSLQS06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICPADS.2006.58 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun_Xue>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Edwin_Hsing-Mean_Sha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mei_Kang_Qiu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Meilin_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zili_Shao>
swrc:pages 375-382 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icpads/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icpads/XueSLQS06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icpads/XueSLQS06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icpads/icpads2006-1.html#XueSLQS06>
rdfs:seeAlso <https://doi.org/10.1109/ICPADS.2006.58>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icpads>
dc:title Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document