Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/icpp/MolkaHSN15
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/icpp/MolkaHSN15
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Hackenberg
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Molka
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Robert_Sch%E2%88%9A%E2%88%82ne
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Wolfgang_E._Nagel
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICPP.2015.83
>
foaf:
homepage
<
https://doi.org/10.1109/ICPP.2015.83
>
dc:
identifier
DBLP conf/icpp/MolkaHSN15
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICPP.2015.83
(xsd:string)
dcterms:
issued
2015
(xsd:gYear)
rdfs:
label
Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Hackenberg
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Daniel_Molka
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Robert_Sch%E2%88%9A%E2%88%82ne
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Wolfgang_E._Nagel
>
swrc:
pages
739-748
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/icpp/2015
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/icpp/MolkaHSN15/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/icpp/MolkaHSN15
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/icpp/icpp2015.html#MolkaHSN15
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICPP.2015.83
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/icpp
>
dc:
title
Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document