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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icpp/NilssonD99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fredrik_Dahlgren>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jim_Nilsson>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICPP.1999.797410>
foaf:homepage <https://doi.org/10.1109/ICPP.1999.797410>
dc:identifier DBLP conf/icpp/NilssonD99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICPP.1999.797410 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fredrik_Dahlgren>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jim_Nilsson>
swrc:pages 246-257 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icpp/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icpp/NilssonD99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icpp/NilssonD99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icpp/icpp1999.html#NilssonD99>
rdfs:seeAlso <https://doi.org/10.1109/ICPP.1999.797410>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icpp>
dc:subject computer architecture, performance evaluation, transaction processing, cache coherence protocols, multiprocessors, databases, load-store sequences, operating systems (xsd:string)
dc:title Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document