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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ics/ZefferRKH06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Erik_Hagersten>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/H%E2%88%9A%E2%80%A2kan_Zeffer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Martin_Karlsson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zoran_Radovic>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1183401.1183438>
foaf:homepage <https://doi.org/10.1145/1183401.1183438>
dc:identifier DBLP conf/ics/ZefferRKH06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1183401.1183438 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label TMA: a trap-based memory architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Erik_Hagersten>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/H%E2%88%9A%E2%80%A2kan_Zeffer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Martin_Karlsson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zoran_Radovic>
swrc:pages 259-268 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ics/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ics/ZefferRKH06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ics/ZefferRKH06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ics/ics2006.html#ZefferRKH06>
rdfs:seeAlso <https://doi.org/10.1145/1183401.1183438>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ics>
dc:subject chip multi processor (CMP), distributed shared memory (DSM), low complexity server design, node coherence checks, server design, simultaneous multi-threading (SMT), software coherence, trap-based memory architecture (TMA) (xsd:string)
dc:title TMA: a trap-based memory architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document