[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icsap/MishraS10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/B._K._Mishra_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sandhya_Save>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICSAP.2010.44>
foaf:homepage <https://doi.org/10.1109/ICSAP.2010.44>
dc:identifier DBLP conf/icsap/MishraS10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICSAP.2010.44 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/B._K._Mishra_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sandhya_Save>
swrc:pages 287-290 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icsap/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icsap/MishraS10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icsap/MishraS10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icsap/icsap2010.html#MishraS10>
rdfs:seeAlso <https://doi.org/10.1109/ICSAP.2010.44>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icsap>
dc:subject Analog circuit designs methodologies, Analog design automation, ASIC, CAD, EDA tools, Op-amps, Simulated Annealing, SPICE, SoC, AMS (xsd:string)
dc:title Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document