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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/icycsee/LiQDWG15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Endong_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jilong_Qin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qinghua_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weifeng_Gong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xu_Ding>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-662-46248-5%5F53>
foaf:homepage <https://doi.org/10.1007/978-3-662-46248-5_53>
dc:identifier DBLP conf/icycsee/LiQDWG15 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-662-46248-5%5F53 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label An On-chip Interconnection QoS Verification Platform of Processor of Large Data for Architectural Modeling Analysis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Endong_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jilong_Qin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qinghua_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weifeng_Gong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xu_Ding>
swrc:pages 439-447 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/icycsee/2015>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/icycsee/LiQDWG15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/icycsee/LiQDWG15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/icycsee/icycsee2015.html#LiQDWG15>
rdfs:seeAlso <https://doi.org/10.1007/978-3-662-46248-5_53>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/icycsee>
dc:title An On-chip Interconnection QoS Verification Platform of Processor of Large Data for Architectural Modeling Analysis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document