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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iecon/ZhangLGZSL23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cong_Zhao_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fanqiang_Gao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiangzheng_Sima>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yaohua_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ye_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zixin_Li>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIECON51785.2023.10312736>
foaf:homepage <https://doi.org/10.1109/IECON51785.2023.10312736>
dc:identifier DBLP conf/iecon/ZhangLGZSL23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIECON51785.2023.10312736 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Full-Scale Hardware-in-the-Loop Real-Time Simulator for Cascaded H-Bridge Inverter With Supercapacitor and DC-DC Stage. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cong_Zhao_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fanqiang_Gao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiangzheng_Sima>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yaohua_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ye_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zixin_Li>
swrc:pages 1-5 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/IECON51785.2023.10312736>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iecon>
dc:title Full-Scale Hardware-in-the-Loop Real-Time Simulator for Cascaded H-Bridge Inverter With Supercapacitor and DC-DC Stage. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document