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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Madhav_Rao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prashanth_H._C.>
foaf:homepage <http://dx.doi.org/doi.org%2F10.5220%2F0012198400003595>
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dc:identifier DBLP conf/ijcci/CR23 (xsd:string)
dc:identifier DOI doi.org%2F10.5220%2F0012198400003595 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Madhav_Rao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prashanth_H._C.>
swrc:pages 278-287 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ijcci/ijcci2023.html#CR23>
rdfs:seeAlso <https://doi.org/10.5220/0012198400003595>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ijcci>
dc:title Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document