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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/imtic/DayoRCC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abdul_Qadeer_Khan_Rajput>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bhawani_Shankar_Chowdhry>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Khalil_Dayo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Narinder_P._Chowdhry>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-89853-5%5F26>
foaf:homepage <https://doi.org/10.1007/978-3-540-89853-5_26>
dc:identifier DBLP conf/imtic/DayoRCC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-89853-5%5F26 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Impact of Cluster Size on Efficient LUT-FPGA Architecture for Best Area and Delay Trade-Off. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abdul_Qadeer_Khan_Rajput>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bhawani_Shankar_Chowdhry>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Khalil_Dayo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Narinder_P._Chowdhry>
swrc:pages 243-252 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/imtic/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/imtic/DayoRCC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/imtic/DayoRCC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/imtic/imtic2008.html#DayoRCC08>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-89853-5_26>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/imtic>
dc:subject Lookup table; FPGA; CLBs; BLE (xsd:string)
dc:title Impact of Cluster Size on Efficient LUT-FPGA Architecture for Best Area and Delay Trade-Off. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document