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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/imw2/ChenLHWL23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chih-Yuan_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hang-Ting_Lue>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Keh-Chung_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tzu-Hsuan_Hsu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Chen_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIMW56887.2023.10145823>
foaf:homepage <https://doi.org/10.1109/IMW56887.2023.10145823>
dc:identifier DBLP conf/imw2/ChenLHWL23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIMW56887.2023.10145823 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chih-Yuan_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hang-Ting_Lue>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Keh-Chung_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tzu-Hsuan_Hsu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Chen_Chen>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/imw2/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/imw2/ChenLHWL23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/imw2/ChenLHWL23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/imw2/imw2023.html#ChenLHWL23>
rdfs:seeAlso <https://doi.org/10.1109/IMW56887.2023.10145823>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/imw2>
dc:title A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document