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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iniscom/TrinhDDNN20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hong-Phong_Nguyen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Quang-Kien_Trinh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Quang-Manh_Duong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thi-Nga_Dao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Van-Thanh_Nguyen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-030-63083-6%5F9>
foaf:homepage <https://doi.org/10.1007/978-3-030-63083-6_9>
dc:identifier DBLP conf/iniscom/TrinhDDNN20 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-030-63083-6%5F9 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Feasibility and Design Trade-Offs of Neural Network Accelerators Implemented on Reconfigurable Hardware. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hong-Phong_Nguyen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Quang-Kien_Trinh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Quang-Manh_Duong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thi-Nga_Dao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Van-Thanh_Nguyen>
swrc:pages 105-123 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iniscom/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iniscom/TrinhDDNN20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iniscom/TrinhDDNN20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iniscom/iniscom2020.html#TrinhDDNN20>
rdfs:seeAlso <https://doi.org/10.1007/978-3-030-63083-6_9>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iniscom>
dc:title Feasibility and Design Trade-Offs of Neural Network Accelerators Implemented on Reconfigurable Hardware. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document