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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/innovations/0001WY24>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ce_Jin_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nathaniel_Young>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R._Ryan_Williams>
foaf:homepage <http://dx.doi.org/doi.org%2F10.4230%2FLIPIcs.ITCS.2024.66>
foaf:homepage <https://doi.org/10.4230/LIPIcs.ITCS.2024.66>
dc:identifier DBLP conf/innovations/0001WY24 (xsd:string)
dc:identifier DOI doi.org%2F10.4230%2FLIPIcs.ITCS.2024.66 (xsd:string)
dcterms:issued 2024 (xsd:gYear)
rdfs:label A VLSI Circuit Model Accounting for Wire Delay. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ce_Jin_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nathaniel_Young>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R._Ryan_Williams>
swrc:pages 66:1-66:22 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/innovations/2024>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/innovations/0001WY24/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/innovations/0001WY24>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/innovations/innovations2024.html#0001WY24>
rdfs:seeAlso <https://doi.org/10.4230/LIPIcs.ITCS.2024.66>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/innovations>
dc:title A VLSI Circuit Model Accounting for Wire Delay. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document