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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iotaas/ZhangLYYW19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bo_Li_0089>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ding_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hongyu_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mao_Yang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhongjiang_Yan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-030-44751-9%5F3>
foaf:homepage <https://doi.org/10.1007/978-3-030-44751-9_3>
dc:identifier DBLP conf/iotaas/ZhangLYYW19 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-030-44751-9%5F3 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label An FPGA Based Reconfigurable MAC Architecture for Universal Short Range Communication Networks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bo_Li_0089>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ding_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hongyu_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mao_Yang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhongjiang_Yan>
swrc:pages 20-36 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/iotaas/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iotaas/ZhangLYYW19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iotaas/ZhangLYYW19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iotaas/iotaas2019.html#ZhangLYYW19>
rdfs:seeAlso <https://doi.org/10.1007/978-3-030-44751-9_3>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/iotaas>
dc:title An FPGA Based Reconfigurable MAC Architecture for Universal Short Range Communication Networks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document