Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ipps/HuangV04
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Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs.
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Behavioral synthesis, critical net, macro, placement, performance
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Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs.
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