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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ipps/Perez-CelisMMUC16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alicia_Morales-Reyes>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Claudia_Feregrino_Uribe>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Mart%E2%88%9A%E2%89%A0nez-Carranza>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Juan_Andr%E2%88%9A%C2%A9s_P%E2%88%9A%C2%A9rez-Celis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ren%E2%88%9A%C2%A9_Cumplido>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIPDPSW.2016.174>
foaf:homepage <https://doi.org/10.1109/IPDPSW.2016.174>
dc:identifier DBLP conf/ipps/Perez-CelisMMUC16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIPDPSW.2016.174 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alicia_Morales-Reyes>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Claudia_Feregrino_Uribe>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Mart%E2%88%9A%E2%89%A0nez-Carranza>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Juan_Andr%E2%88%9A%C2%A9s_P%E2%88%9A%C2%A9rez-Celis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ren%E2%88%9A%C2%A9_Cumplido>
swrc:pages 156-161 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/IPDPSW.2016.174>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ipps>
dc:title An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document