Partitioning regular grid applications with irregular boundaries for cache-coherent multiprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ipps/ZengA95
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1995
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Partitioning regular grid applications with irregular boundaries for cache-coherent multiprocessors.
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multiprocessing systems; message passing; partitioning regular grid applications; irregular boundaries; cache-coherent multiprocessors; regular grid; domain decomposition techniques; interprocessor communication; message passing multiprocessors; false coherency traffic; cache line; coalescing algorithm; domain decomposition algorithm; Indian Ocean circulation application; KSR1 multiprocessor; coherency traffic
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Partitioning regular grid applications with irregular boundaries for cache-coherent multiprocessors.
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