Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ipps/ZhuoMP05
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Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/ipps/ZhuoMP05
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Gerald_R._Morris
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ling_Zhuo
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FIPDPS.2005.165
>
foaf:
homepage
<
https://doi.org/10.1109/IPDPS.2005.165
>
dc:
identifier
DBLP conf/ipps/ZhuoMP05
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FIPDPS.2005.165
(xsd:string)
dcterms:
issued
2005
(xsd:gYear)
rdfs:
label
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Gerald_R._Morris
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ling_Zhuo
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna
>
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/ipps/2005
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/ipps/ZhuoMP05/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/ipps/ZhuoMP05
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/ipps/ipdps2005.html#ZhuoMP05
>
rdfs:
seeAlso
<
https://doi.org/10.1109/IPDPS.2005.165
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/ipps
>
dc:
title
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document