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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/irps/JiangSKPSP19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hai_Jiang_0005>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hyun-Chul_Sagong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinju_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junekyun_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sangchul_Shin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sangwoo_Pae>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIRPS.2019.8720409>
foaf:homepage <https://doi.org/10.1109/IRPS.2019.8720409>
dc:identifier DBLP conf/irps/JiangSKPSP19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIRPS.2019.8720409 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hai_Jiang_0005>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hyun-Chul_Sagong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinju_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junekyun_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sangchul_Shin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sangwoo_Pae>
swrc:pages 1-5 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/irps/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/irps/JiangSKPSP19/dblp>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/irps/irps2019.html#JiangSKPSP19>
rdfs:seeAlso <https://doi.org/10.1109/IRPS.2019.8720409>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/irps>
dc:title Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document