Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory.
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/irps/LinKCLHTLLCWL18
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/C._H._Cheng
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/C._W._Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Chih-Yuan_Lu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ijen_Huang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/K._C._Chen
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/S._H._Ku
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/T._C._Lu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/T._W._Lin
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tahui_Wang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/W._P._Lu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Wen-Jer_Tsai
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FIRPS.2018.8353679
>
foaf:
homepage
<
https://doi.org/10.1109/IRPS.2018.8353679
>
dc:
identifier
DBLP conf/irps/LinKCLHTLLCWL18
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FIRPS.2018.8353679
(xsd:string)
dcterms:
issued
2018
(xsd:gYear)
rdfs:
label
Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/C._H._Cheng
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/C._W._Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Chih-Yuan_Lu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ijen_Huang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/K._C._Chen
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/S._H._Ku
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/T._C._Lu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/T._W._Lin
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tahui_Wang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/W._P._Lu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Wen-Jer_Tsai
>
swrc:
pages
6-1
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/irps/2018
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/irps/LinKCLHTLLCWL18/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/irps/LinKCLHTLLCWL18
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/irps/irps2018.html#LinKCLHTLLCWL18
>
rdfs:
seeAlso
<
https://doi.org/10.1109/IRPS.2018.8353679
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/irps
>
dc:
title
Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document