Improving cache Performance Through Tiling and Data Alignment.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/irregular/PandaNDN97
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/irregular/PandaNDN97
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Alexandru_Nicolau
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Nakamura
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Nikil_D._Dutt
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Preeti_Ranjan_Panda
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1007%2F3-540-63138-0%5F16
>
foaf:
homepage
<
https://doi.org/10.1007/3-540-63138-0_16
>
dc:
identifier
DBLP conf/irregular/PandaNDN97
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1007%2F3-540-63138-0%5F16
(xsd:string)
dcterms:
issued
1997
(xsd:gYear)
rdfs:
label
Improving cache Performance Through Tiling and Data Alignment.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Alexandru_Nicolau
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Nakamura
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Nikil_D._Dutt
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Preeti_Ranjan_Panda
>
swrc:
pages
167-185
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/irregular/1997
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/irregular/PandaNDN97/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/irregular/PandaNDN97
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/irregular/irregular97.html#PandaNDN97
>
rdfs:
seeAlso
<
https://doi.org/10.1007/3-540-63138-0_16
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/irregular
>
dc:
title
Improving cache Performance Through Tiling and Data Alignment.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document