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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isca/AziziMLPH10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aqeel_Mahesri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Benjamin_C._Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mark_Horowitz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Omid_Azizi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjay_J._Patel>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1815961.1815967>
foaf:homepage <https://doi.org/10.1145/1815961.1815967>
dc:identifier DBLP conf/isca/AziziMLPH10 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1815961.1815967 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aqeel_Mahesri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Benjamin_C._Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mark_Horowitz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Omid_Azizi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjay_J._Patel>
swrc:pages 26-36 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isca/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isca/AziziMLPH10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isca/AziziMLPH10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isca/isca2010.html#AziziMLPH10>
rdfs:seeAlso <https://doi.org/10.1145/1815961.1815967>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isca>
dc:subject co-optimization, design space exploration, design trade-offs, energy efficiency, microarchitecture, optimization (xsd:string)
dc:title Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document