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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isca/HongK09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hyesoon_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sunpyo_Hong>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1555754.1555775>
foaf:homepage <https://doi.org/10.1145/1555754.1555775>
dc:identifier DBLP conf/isca/HongK09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1555754.1555775 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hyesoon_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sunpyo_Hong>
swrc:pages 152-163 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isca/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isca/HongK09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isca/HongK09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isca/isca2009.html#HongK09>
rdfs:seeAlso <https://doi.org/10.1145/1555754.1555775>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isca>
dc:subject GPU architecture, analytical model, cuda, memory level parallelism, performance estimation, warp level parallelism (xsd:string)
dc:title An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document